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C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
* Dedicated clock buffer power pins for reduced noise, crosstalk and jitter * Input clock frequency of 25 MHz to 33 MHz * Output frequencies of XINx1, XINx2, XINx3 and XINx4 * One output bank of 5 clocks. * One REF XIN clock output. * SMBus clock control interface for individual clock disabling and SSCG control * Output clock duty cycle is 50% ( 5%) * < 250 ps skew between output clocks within a bank * Output jitter <175 ps * Spread Spectrum feature for reduced electromagnetic interference (EMI) * OE pin for entire output bank enable control and testability * 28-pin SSOP and TSSOP packages Table 1. Test Mode Logic Table[1] Input Pins OE HIGH HIGH HIGH HIGH LOW S1 LOW LOW HIGH HIGH X S0 LOW HIGH LOW HIGH X Output Pins CLK XIN 2 * XIN 3 * XIN 4 * XIN REF XIN XIN XIN XIN
Three-state Three-state
Block Diagram
Pin Configuration
REF
1 2 3 4 5 6
28 27 26 25 24 23
SDATA SCLK VSS VDDP CLK0 CLK1 CLK2 VSS VDDP CLK3 CLK4 VDDA VSS SSCG#
SSCG#
SSCG Logic /N
1 0
CLK0 CLK1 CLK2 CLK3 CLK4 OE GOOD# REF
VDD XIN XOUT VSS S0 S1 GOOD# VSS IA0 IA1 IA2 VDDA OE
C9531
XIN XOUT
7 8 9 10 11 12 13 14
22 21 20 19 18 17 16 15
SDATA SCLK IA(0:2) S(0,1)
I 2C Control Logic
Note: 1. XIN is the frequency of the clock on the device's XIN pin.
Cypress Semiconductor Corporation Document #: 38-07034 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised May 12, 2003
C9531
Pin Description[3]
Pin[2] 3 4 1 14* 24, 23, 22, 19, 18 8 XIN XOUT REF OE CLK(0:4) GOOD# Name PWR[4] VDDA VDDA VDD VDD VDDP VDD I/O I O O I O O Description Crystal Buffer Input Pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. Crystal Buffer Output Pin. Connects to a crystal only. When a Can Oscillator is used or in test mode, this pin is kept unconnected. Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz. Output Enable for Clock Bank. Causes the CLK (0:4) output clocks to be in a three-state condition when driven to a logic low level. A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. When his output signal is a logic low level, it indicates that the output clocks of the bank are locked to the input reference clock. This output is latched. Clock Bank Selection Bits. These control the clock frequency that will be present on the outputs of the bank of buffers. See table on page one for frequency codes and selection values. 3.3V common power supply pin for all PCI clocks CLK (0:4). SMBus Address Selection Input Pins. See Table 3 on page 3. Spread Spectrum Clock Generator. Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. Data for the Internal SMBus Circuitry. See Table 3 on page 3. Clock for the Internal SMBus Circuitry. See Table 3 on page 3. Power for Internal Analog Circuitry. This supply should have a separately decoupled current source from VDD. Power supply for internal core logic. Ground pins for the device.
6*, 7*
S(0,1)
VDD
I
20, 25 10*, 11*, 12* 15*
VDDP IA(0:2) SSCG# VDD VDD
PWR I I
28 27 13, 17 2 5, 9, 16, 21, 26
SDATA SCLK VDDA VDD VSS
VDD VDD
I/O I I PWR PWR
Notes: 2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. A bypass capacitor (0.1F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts block write a operations from the controller. The bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The C9531 does not support the Block Read function. The block write protocol is outlined in Table 2. The addresses are listed in Table 3.
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C9531
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description
Table 3. SMBus Address Selection Table SMBus Address of the Device DE DC DA D8 D6 D4 D0 D2 IA0 Bit (Pin 10) 0 1 0 1 0 1 0 1 IA1 Bit (Pin 11) 0 0 1 1 0 0 1 1 IA2 Bit (Pin 12) 0 0 0 0 1 1 1 1
Serial Control Registers
Byte 0: Output Register Bit 7 6 5 4 3 @Pup 1 0 1 0 0 Name TESTEN SSEN SSSEL S1 S0 Description Test Mode Enable. 1 = Normal operation, 0 = Test mode Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0 = OFF, 1= ON SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Page 3 of 10
Document #: 38-07034 Rev. *D
C9531
Byte 0: Output Register (continued) 2 1 0 0 0 1 HWSEL Not used Not used Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5 Byte0, bit6 0 0 1 1 Table 5. Test Table Outputs Test Function Clock Frequency Byte 1: CPU Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 REFEN Name Reserved Reserved REF Output Enable 0 = Disable, 1= Enable Reserved Reserved Reserved Reserved Reserved Description CLK XIN/4 REF XIN Note XIN is the frequency of the clock that is present on the XIN input during test mode. Byte0, bit5 0 1 0 1 Frequency generated from XIN Spread @ -1.0% Spread @ -0.5% Description Frequency generated from second PLL
Byte 2: PCI Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 18 19 22 23 24 Name Reserved Reserved Reserved CLK4 Output Enable 0 = Disable, 1= Enable CLK3 Output Enable 0 = Disable, 1= Enable CLK2Output Enable 0 = Disable, 1= Enable CLK1 Output Enable 0 = Disable, 1= Enable CLK0 Output Enable 0 = Disable, 1= Enable Description
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C9531
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state condition by bringing their relevant OE pins to a logic low state. This transition to and from a three-state and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. The output enable pin contains an internal pull-up resistor that will insure that a logic 1 is maintained and sensed by the device if no external circuitry is connected to this pin. control signals is determined by the SMBus register Byte 0 bit 0. At initial power up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the device's S(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection S(0,1) must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (B0b0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Bytes 0 bits 3 and 4 to control the output clock's frequency. The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these
CL =
where: CXTAL CXINFTG CXINPCB CXINDISC
(CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
= The load rating of the crystal. = The clock generators XIN pin effective device internal capacitance to ground. = The effective capacitance to ground of the crystal to device PCB trace. = Any discrete capacitance that is placed between the XIn pin and ground.
CXOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground. CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace. CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
CXINPCB CXOUTPCB
CXINDISC CXOUTDISC
XIN CXINFTG CXOUTFTG
XOUT
Clock Generator
As an example and using this formula for this data sheet's device, a design that has no discrete loading capacitors (CDISC) and each of the crystal device PCB traces has a capacitance (CPCB) to ground of 4 pF (typical value) would calculate as:
CL =
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
= 40 x 40 40 x 40
=
1600 = 20 pF. 80
Therefore, to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20 pF.
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C9531
Spread Spectrum Clocking
Down Spread Description Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread Bandwidth). This technique allows the distribution of the undesirable electromagnetic energy (EMI) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. As the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all of its harmonics. In this device Spread Spectrum is enabled externally through pin 15 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Spread spectrum is enabled externally when the SSCG# pin is low. This pin has an internal device pull up resistor, which causes its state to default to a HIGH (spread spectrum modulation disabled) unless externally forced to a low. It may also be enabled by programming SMBus Byte 0 Bit 0 LOW (to enable SMBus control of the function) and then programming SMBus byte 0 bit 6 low to set the feature active.
S p re a d o ff
S p re a d o n
C e n te r F re q u e n c y , S p re a d o n
C e n te r F r e q u e n c y , S p re a d o ff
Figure 1. Spread Spectrum Table 6. Spectrum Spreading Selection Output Clock Frequency 33.3 MHz (XIN) 66.6 MHz (XIN*2) 100.0 MHz (XIN*3) 133.3 MHz (XIN*4) Table[5] % of Frequency Spreading SMBus Byte 0 Bit 5 = 0 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) SMBus Byte 0 Bit 5 = 1 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) Mode Down Spread Down Spread Down Spread Down Spread
Note: 5. When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100-MHz output clock frequency will sweep through a spectral range from 99 to 100 MHz.
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C9531
Absolute Maximum Conditions
Parameter VDD,VDDP VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. V-0 1 Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD, VDDP, VDDA VILI2C VIHI2C VIL VIH IIL VOL VOH IOZ CIN COUT LIN CXTAL VXIH VXIL IDD IPD Description 3.3V Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current At 133 MHz and all outputs loaded per Table 7 PD# Asserted From XIN and XOUT pins to ground except Pull-ups or Pull-downs 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3V 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS-0.5 2.0 -5 - 2.4 -10 2 3 - 32 0.7VDD 0 - - Max. 3.465 1 - 0.8 VDD+0. 5 5 0.4 - 10 5 6 7 38 VDD 0.3VDD 300 1 Unit V V - V V A V V A pF pF nH pF V V mA mA
AC Electrical Specifications
Parameter Crystal TDC XINFREQ TR / TF Description XIN Duty Cycle XIN Frequency XIN Rise and Fall Times Condition The device will operate reliably with input duty cycles up to 30/70% When Xin is driven from an external clock source Measured between 0.3VDD and 0.7VDD Min. Max. Unit
45 25 -
55 33.3 10.0
% MHz ns
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C9531
AC Electrical Specifications (continued)
Parameter TCCJ LACC CLK TDC TPERIOD33 TPERIOD66 TPERIOD100 TPERIOD133 TR / TF TSKEW TCCJ REF TDC TR / TF TCCJ Description XIN Cycle to Cycle Jitter Long Term Accuracy CLK Duty Cycle 33-MHz CLK Period 66-MHz CLK Period 100-MHz CLK Period 133-MHz CLK Period CLK Rise and Fall Times CLK Cycle to Cycle Jitter REF Duty Cycle REF Rise and Fall Times REF Cycle to Cycle Jitter Over 150 ms Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V 45 29.5 14.5 9.5 7.0 0.5 - - 45 1.0 - - - - Condition As an average over 1s duration Min. - Max. 500 300 55 30.5 15.5 10.5 8.0 2.0 250 175 55 4.0 750 10.0 10.0 3.0 Unit ps ppm % ns ns ns ns ns ps ps % ns ps ns ns ms
Any CLK to Any CLK Clock Skew Measurement at 1.5V
ENABLE/DISABLE and SET-UP tpZL,tpZH Output Enable Delay (all outputs) tpLZ,tpZH TSTABLE Output Disable Delay (all outputs) Clock Stabilization from Power-up
Test and Measurement Set-up
3 . 3 V S ig n a ls
tD C
-
Output under Test Probe
2 .4 V
3 .3 V
Load Cap
1 .5 V
0 .4 V 0V
Tr
Tf
Lumped Load
LVTTL Signaling Figure 2. Test and Measurement Set-up
Table 7. Loading Output Name CLK REF Max Load (in pF) 30 20
Ordering Information
Part Number IMIC9531CY IMIC9531CYT IMIC9531CT IMIC9531CTT Document #: 38-07034 Rev. *D Package Type 28-Pin SSOP 28-Pin SSOP - Tape and Reel 28-Pin TSSOP 28-Pin TSSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Page 8 of 10
C9531
Package Drawing and Dimension
28-lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
28-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z29
51-85120-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07034 Rev. *D
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges..
C9531
Document History Page Document Title: C9531 PCIX I/O System Clock Generator with EMI Control Features Document #: 38-07034 REV. ** *A ECN NO. 106962 114504 Issue Date 06/12/02 08/15/02 Orig. of Change IKA DMG Description of Change Convert from IMI to Cypress Converted from Word to Frame Corrected Ordering Information by adding tape and reel option IMIC9531CYT and IMIC9531CTT to match the Devmaster Corrected the Package Drawing and Dimension from 28 TSOP to 28 TSSOP Removed the read function in the SMBus Area Added power up requirements to maximum ratings information Fixed DC and AC table to match characteristic data Added 25-MHz Operation
*B *C *D
120839 122727 126597
11/25/02 12/14/02 05/14/03
RGL/ DMG RBI RGL
Document #: 38-07034 Rev. *D
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